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課程類別：半導體技術 (執行單位 : 財團法人自強工業科學基金會)
| 課程名稱 | 課程介紹 | 收費方式 |
|---|---|---|
| 【竹科管理局補助課程】VLSI積體電路ESD防護佈局設計與佈局專利分析**報名已截止** | 1.ESD Protection Architecture - ESD Introduction and Stress Modes - ESD Failure Mechanisms - ESD Protection Architecture in Chip Level 2.How to Do a Good Layout for ICs ? - Design Rules for ESD - Design Rules for Latch-up - ESD Protection Component: Resistor - ESD Protection Component: Capacitor - ESD Protection Component: Diode - ESD Protection Component: MOSFET 3.Whole Chip ESD Protections - Input Pins ESD Protection - Output Pins ESD Protection - Power Pins ESD Protection - Mixed-mode ESD Protections 4.Patents Study on ESD/LU Protections by Layout Techniques - Protection Patents in the Layout Considerations 5.ESD Protection-Networks in ICs |
收費 * 報名截止日：2024/08/01* 開課日期：2024/08/03~2024/08/10 |