 課程名稱 |
【竹科管理局補助課程】VLSI積體電路ESD防護佈局設計與佈局專利分析 |
| 課程內容 |
1.ESD Protection Architecture - ESD Introduction and Stress Modes - ESD Failure Mechanisms - ESD Protection Architecture in Chip Level 2.How to Do a Good Layout for ICs ? - Design Rules for ESD - Design Rules for Latch-up - ESD Protection Component: Resistor - ESD Protection Component: Capacitor - ESD Protection Component: Diode - ESD Protection Component: MOSFET 3.Whole Chip ESD Protections - Input Pins ESD Protection - Output Pins ESD Protection - Power Pins ESD Protection - Mixed-mode ESD Protections 4.Patents Study on ESD/LU Protections by Layout Techniques - Protection Patents in the Layout Considerations 5.ESD Protection-Networks in ICs |
| 先修課程 |
| 上課日期 | 上課時段 | 授課老師 | 報名截止日 | 上課地點 | 報名 | 課程費用 |
|---|---|---|---|---|---|---|
| 20240803-20240810 | 週六，09:00-17:30 | 自強基金會專業講師 | 20240801 | 清華大學第四綜合大樓 | 報名已截止 | 1500 |